Back to Flagship Projects

The Open Memory Initiative (OMI)

Building an open-source DDR4 UDIMM reference design with documentation-first methodology.

Last updated: March 1, 2026

Why Open Memory?

The memory module industry lacks transparency. From schematic references to signal integrity guidelines, much of the knowledge is locked behind NDAs or proprietary documentation. The Open Memory Initiative was founded to change this.

OMI is building a fully transparent, reproducible DDR4 UDIMM reference design that anyone can study, modify, and manufacture.

Architecture Decision Records

Every major design decision is documented through Architecture Decision Records (ADRs) before implementation begins. This methodology ensures traceability, reproducibility, and educational value.

ADR-001: DDR4 UDIMM Form Factor Selection

Context: Choosing between SO-DIMM, UDIMM, RDIMM, and LRDIMM form factors.

Decision: UDIMM was selected as the reference platform due to its ubiquity in desktop and entry-level server systems, simpler topology (no register buffer), and lower barrier to entry for contributors.

ADR-002: KiCad as Primary EDA Tool

Context: Evaluating EDA tools for schematic capture and PCB layout.

Decision: KiCad was chosen for its open-source license, active community, and growing industry adoption. This ensures the entire toolchain remains freely accessible.

ADR-003: Documentation-First Methodology

Context: Defining the development workflow for hardware design.

Decision: All design work follows a staged approach: research, document, design, validate. Architecture decisions are recorded in ADRs before any schematic work begins.

Design Process

Power Distribution Network (PDN)

The DDR4 UDIMM requires multiple voltage rails: VDD (1.2V), VDDQ (1.2V), VPP (2.5V), and VTT (0.6V). The PDN design focuses on decoupling strategy, plane impedance, and bulk capacitor placement.

Address/Command/Clock

The address, command, and clock routing follows JEDEC timing specifications with careful attention to fly-by topology for clock and address signals. Impedance matching and length matching are critical in this domain.

Data Byte Lanes

Each data byte lane consists of 8 data bits plus a DQS strobe pair. The routing strategy prioritizes matched lengths within each byte lane while allowing controlled skew between byte lanes.

Educational Content

OMI includes 10+ educational chapters covering:

Tech Stack

What's Next